tag nrho: image matching

 
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Algorithm-Based Low Power VLSI Architecture For 2d-Mesh Video Object Motion Tracking

The new VLSI architecture for video object (VO) motion tracking uses a novel hierarchical adaptive structured mesh topology. Tus qauv mesh muaj ib qhov teeb meem loj txo rau cov khoom uas piav cov mesh topology. The motion of the mesh nodes represents the deformation of the VO. Motion compensation is performed using a multiplication-free algorithm for affine transformation, significantly reducing the decoder architecture complexity. Pipelining the affine unit contributes a considerable power saving. The VO motion-tracking architecture is based on a new algorithm. It consists of two main parts: a video object motion-estimation unit (VOME) and a video object motion-compensation unit (VOMC). The VOME processes two consequent frames to generate a hierarchical adaptive structured mesh and the motion vectors of the mesh nodes. It implements parallel block matching motion-estimation units to optimize the latency. The VOMC processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion-compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. Tus architecture muaj tau prototyped siv saum-down low-power tsim methodology. Performance analysis shows that this processor can be used in online object-based video applications such as MPEG-4 and VRML

Wael Badawy thiab Magdy Bayoumi, "Algorithm-Based Low Power VLSI Architecture For 2d-Mesh Video Object Motion Tracking,” The IEEE Transaction on Circuits and Systems for Video Technology, Vol. 12, No. 4, Lub Plaub Hlis Ntuj 2002, pps. 227-237

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Ib Affine raws li Algorithm thiab SIMD Architecture rau yees duab Compression uas tsis muaj bit-rate applications

Daim ntawv no tam sim no ib tug tshiab affine kuas algorithm thiab SIMD architecture rau yees duab compression uas tsis muaj nqi tsawg daim ntawv thov. Cov lus algorithm siv rau mesh kuas tsab ntawv tsa suab kwv yees thiab nws yog lub npe hu ua mesh kuas square-matching algorithm (MB-SMA). The MB-SMA is a simplified version of the hexagonal matching algorithm [1]. In this algorithm, right-angled triangular mesh is used to benefit from a multiplication free algorithm presented in [2] computing lub parameters. Cov lus algorithm muaj tsawg dua cov hexagonal matching algorithm thaum nws ua yuav luag tib ncov signal-to-nrov piv (PSNR) qhov tseem ceeb. Tus MB-SMA outperforms feem ntau siv tsab ntawv tsa suab kwv yees algorithms ntawd computational nqi, efficiency thiab yees duab zoo (i.e., PSNR). Tus MB-SMA yog DVR siv ib SIMD architecture uas ib tug xov tooj ntawm txheej txheem muaj tau embedded nrog SRAM blocks los utilize tus loj nco bandwidth. Cov lus architecture xav tau 26.9 MS mus txheej txheem ib CIF yees duab ncej. Yog li ntawd, vim, nws yuav ua tau ntaub ntawv 37 CIF frames/s. Cov lus architecture muaj tau prototyped siv Taiwan Semiconductor Manufacturing tuam txhab (TSMC) 0.18-μm CMOS tshuab thiab cov embedded SRAMs muaj tau generated siv Virage Logic nco compiler.

Luam tawm nyob rau hauv:

Circuits and Systems for Video Technology, IEEE Transactions rau (ntim:16 , Qhov no: 4 )

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Mohammed Sayed , Wael Badawy, “Ib Affine raws li Algorithm thiab SIMD Architecture rau yees duab Compression uas tsis muaj bit-rate applications“, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, Qhov no 4, pps. 457-471, Lub Plaub Hlis Ntuj 2006. abstract