Tag: Performance analysis
A Low Power VLSI Architecture for Mesh-based Video Motion Tracking
This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and uses a parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML.
Wael Badawy and Magdy Bayoumi, “A Low Power VLSI Architecture for Mesh-based Video Motion Tracking,” The IEEE Transactions on Circuits and Systems II, Vol. 49, July 2002, pp. 488-504.
DeFET: A Novel CMOS Electric-Field Sensor for Lab-on-a-Chip and Biomedical Applications
This paper presents a novel CMOS electric-field sensor, it is called the “differential electric-field sensitive field-effect transistor” (DeFET), which is based on a standard 0.18-mum Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. The DeFET shows a sensitivity of 51.7 mV/(V/mum). This paper also describes the DeFET’s theory of operation in addition to the experimental and simulation results that confirm the DeFET’s theory of operation. Some applications of the DeFET in the area of lab on a chip and biomedical are also presented
- 1027 – 1037
- ISSN :
- INSPEC Accession Number:
- Date of Publication :
- Aug. 2006
- Date of Current Version :
- 24 July 2006
- Issue Date :
- Aug. 2006
- Sponsored by :
- IEEE Sensors Council
Link to the list of other Peer Journal Publications
Yehya Ghallab, Wael Badawy, “DeFET: A Novel CMOS Electric-Field Sensor for Lab-on-a-Chip and Biomedical Applications,” IEEE Sensors Journal, Volume 6, Issue: 4, Aug. 2006, pp. 1027 – 1037.