A New Call Admission and bandwidth reservation Scheme for Future Wireless Networks
The paper proposes a new scheme for call admission and bandwidth reservation for the next generation wireless networks. The proposed scheme OPBR (optimal cell partition based bandwidth reservation) does an optimal partitioning of the cell to give high degree of call admission and successful handoff. In addition it offers effective bandwidth utilization and guarantee QoS. The performance of the scheme is done by analytical modeling and simulation experiments. A comparison with two different schemes (PBR and adaptive reservation) shows desirable results can be achieved by proposed scheme with better performance for various QoS parameters.
Download A New Call Admission and Bandwidth Reservation Scheme for Future Wireless Networks
Mehboob Alam, Wael Badawy, Graham Jullien, “A New Call Admission and bandwidth reservation Scheme for Future Wireless Networks,” WSEAS Transactions on Communications, Vol. 1, Issue 1, pp. 197-203, ISSN 1109-2742
Sensing methods of Dielectrophories from Bulky Instruments to Lab-on-a-chip
Recently, the sensing methods for dielectrophoresis (DEP) have been changed from bulky instruments to lab-on-a-chip. Lab-on-a-chip based the dielectrophoresis phenomenon holds the promise to give biology the advantage of miniaturization for carrying out complex experiments. However, until now, there is an unmet need for lab-on-a-chip to effectively deal with the biological systems at the cell level.
Published in:
Circuits and Systems Magazine, IEEE (Volume:4 , Issue: 3 )
- Page(s):
- 5 – 15
- ISSN :
- 1531-636X
- INSPEC Accession Number:
- 8135939
- DOI:
- 10.1109/MCAS.2004.1337805
- Date of Publication :
- Third Quarter 2004
- Date of Current Version :
- 04 October 2004
- Issue Date :
- Third Quarter 2004
- Sponsored by :
- IEEE Circuits and Systems Society
- Publisher:
- IEEE
Yehya H. Ghallab, and Wael Badawy, “Sensing methods of Dielectrophories from Bulky Instruments to Lab-on-a-chip,” IEEE Circuit and Systems, Vol. 4, Issue 3, 2004
A Low Power Architecture for HASM Motion Tracking
This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.
The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.
The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.
The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.
Wael Badawy and Magdy Bayoumi “A Low Power Architecture for HASM Motion Tracking,” The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, May 2004, Vol. 37, Issue 1, pp. 111-127
Architectures for Finite Radon Transform
Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.
Published in:
Electronics Letters (Volume:40 , Issue: 15 )
- Page(s):
- 931 – 932
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 8068176
- DOI:
- 10.1049/el:20040566
- Date of Publication :
- 22 July 2004
- Date of Current Version :
- 02 August 2004
- Issue Date :
- 22 July 2004
- Sponsored by :
- Institution of Engineering and Technology
- Publisher:
- IET
C. A. Rahman and W. Badawy, “Architectures for Finite Radon Transform“, The IEE Electronics Letters, Vol. 40, Issue 15, July 2004, pp. 931-932.
A Computational RAM (C-RAM) Architecture for Real-Time Mesh-Based Video Motion Tracking: Part II Motion Compensation
This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. In Part 1, the motion estimation part of the proposed architecture is presented. Here in Part 2, a new C-RAM mesh-based motion compensation architecture is presented. The input data to the architecture is the mesh nodes motion vectors and the reference frame and the output data is the compensated (i.e., predicted) frame. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The architecture computes the affine parameters using a multiplication-free algorithm. The reference and current frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion compensation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. Using 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 0.59 ms, which means it can process up to 1694 frames per second. The core area of the proposed motion compensation architecture is 28.04 mm2 and it consumes 31.15 mW.
Mohammed Sayed and Wael Badawy, “A Computational RAM (C-RAM) Architecture for Real-Time Mesh-Based Video Motion Tracking: Part II Motion Compensation,” Journal of Circuits, Systems and Computer, Vol. 13, Issue 6, December 2004, pp. 1217-1232.
A Computational RAM (C-RAM) Architecture for Real-Time Mesh-Based Video Motion Tracking: Part I Motion Estimation,
This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. The motion tracking consists of two operations: mesh-based motion estimation and compensation. The proposed motion estimation architecture is presented in Part 1 and the proposed motion compensation architecture is presented in Part 2. The motion estimation architecture stores two frames and computes motion vectors for a regular triangular mesh structure as defined by MPEG-4 Part 2.1 The motion estimation architecture uses the block-matching algorithm (BMA) to estimate the vertical and horizontal motion vectors for each mesh node. Parallel and pipelined implementations have been used to overcome the huge computational requirements of the motion estimation process. The two frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion estimation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. At 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 1.48 ms, which means it can process up to 675 frames per second. The core area of the proposed motion estimation architecture is 24.58 mm2 and it consumes 46.26 mW.
Read More: https://www.worldscientific.com/doi/abs/10.1142/S0218126604001921
Mohammed Sayed and Wael Badawy, “A Computational RAM (C-RAM) Architecture for Real-Time Mesh-Based Video Motion Tracking: Part I Motion Estimation,” Journal of Circuits, Systems and Computers, Vol. 13, Issue 6, December 2004, pp. 1203-1216.
A Real-time Multiple-cell Tracking Platform for Dielectrophoresis (DEP) based Cellular Analysis,
There is an increasing demand from biosciences to develop new and efficient techniques to assist in the preparation and analysis of biological samples such as cells in suspension. A dielectrophoresis (DEP)-based characterization and measurement technique on biological cells opens up a broader perspective for early diagnosis of diseases. An efficient real-time multiple-cell tracking platform coupled with DEP to capture and quantify the dynamics of cell motion and obtain cell viability information is presented. The procedure for tracking a single DEP-levitated Canola plant protoplast, using the motion-based segmentation algorithm hierarchical adaptive merge split mesh-based technique (HAMSM) for cell identification, has been enhanced for identifying and tracking multiple cells. The tracking technique relies on the deformation of mesh topology that is generated according to the movement of biological cells in a sequence of images that allows the simultaneous extraction of the biological cell from the image and the associated motion characteristics. Preliminary tests were conducted with yeast cells and then applied to a cancerous cell line subjected to DEP fields. Characteristics, such as cell count, velocity and size, were individually extracted from the tracked results of the cell sample. Tests were limited to eight yeast cells and two cancer cells. A performance analysis to assess tracking accuracy, computational effort and processing time was also conducted. The tracking technique employed on model intact cells in DEP fields proved to be accurate, reliable and robust.
Brinda Prasad, K. Kaler and Wael Badawy, “A Real-time Multiple-cell Tracking Platform for Dielectrophoresis (DEP) based Cellular Analysis,” Measurement Science and Technology, Vol. 6, April 2005, pp. 909-924.
I am the BRAND on online search engines
For the last 10+ years, many companies approached me and promise a better ranking for Google search and to get my link in the first page. This is the goal of many companies, which may be good.
Over the last two weeks, I was building my website and I deployed my experience on website development and social media.
I was able to get my name in all links in the first 2 pages of google search and at least 8 out of 10 links in pages 3 – 12 of the search engine. I am now the brand who can appear 105 times out of 120 result link.
I was able to be dominating the top 27search result out About 130,000 results, It basically demonstrate and I am listed in 134 out of the top 160 and I should conclude that I am the BRAND.
Similar results are achieved on Yahoo and BING, and the following images. The following 17 images prove that my name dominates the top 16 pages search result and the following 2 images show the first pages of Ping and Yahoo search,
Can you do me a favour, search my name “Wael Badawy“ from your end on google.com, yahoo.com and bing.com and write in the comment if you find me that I am the Brand in your search
A new time distributed DCT architecture for MPEG-4 hardware reference model
This paper presents the design of a new time distributed architecture (TDA) which outlines the architecture (ISO/IEC JTC1/SC29/WG11 MPEG2002/M8565) submitted to MPEG4 Part9 committee and included in the ISO/IEC JTC1/SC29/WG11 MPEG2002/9115N document. The proposed TDA optimizes the two-dimensional discrete cosine transform (2-D-DCT) architecture performance. It uses a time distribution mechanism to exploit the computational redundancy within the inner product computation module. The application specific requirements of input, output and coefficients word length are met by scheduling the input data. The coefficient matrix uses linear mappings to assign necessary computation to processor elements in both space and time domains. The performance analysis shows performance savings in excess of 96% as compared to the direct implementation and more than 71% as compared to other optimized application specific architectures for DCT.
Published in:
Circuits and Systems for Video Technology, IEEE Transactions on (Volume:15 , Issue: 5 )
- Page(s):
- 726 – 730
- ISSN :
- 1051-8215
- INSPEC Accession Number:
- 8422879
- DOI:
- 10.1109/TCSVT.2005.846429
- Date of Publication :
- May 2005
- Date of Current Version :
- 02 May 2005
- Issue Date :
- May 2005
- Sponsored by :
- IEEE Circuits and Systems Society
- Publisher:
- IEEE
Alam, M.; Badawy, W.; Jullien, G.; “A new time distributed DCT architecture for MPEG-4 hardware reference model,” IEEE Circuits and Systems for Video Technology, Volume 15, Issue 5, May 2005, pp. 726 – 730.
21 site is infringing my book copyright
I was searching the internet and I found that 21 site is infringing my book copy right including the cover.
